Silicon Photonics’ Shift: Still Cost/Loss Issues

Published on
blog 1486467782 79

The lead article in the September 1969 issue of the Bell System Technical Journal was written by Stewart E. Miller, entitled “Integrated Optics: An Introduction,” which framed “a proposal for a miniature laser beam circuitry” along with the promise of “economy should ultimately result.” Close to a half of a century later, even with a severe bastardization of the original definition in recent times, as the electronics have been excluded from the chip (even Luxtera had to abandon its vision of “CMOS photonics” at 100-gig), challenges remain with expensive cost along with poor performance. While perhaps the best way to characterize Silicon Photonics (SP) today is the use of a continuous wave light source and a modulator in Si, as opposed to integrated optics (passive AWGs or PLCs), the concept of light going into a waveguide with SP, and pulling it out, results in an incredibly high Insertion Loss (IL).

So, for suppliers, such as Mellanox Technologies, the photonic chip (PIC) and the electronic chip (EIC) are each on different technologies. The latter is flipped on to the former to mitigate the cost and yield matters.

With the IL factor on SPs, vendors will be struggling, perhaps indefinitely, to meet LR4, 10-kiometer 100G solutions, in which high launch power and low loss is required. Thus, traditional players, such as Finisar and Oclaro, should continue to maintain their businesses without worrying about the threat from SPs.

Regarding designs for the very long term, electrical engineers working on ASICs are getting anxious as it relates to 50G I/Os. When deeply analyzing the electrical channels on PAM-4, these folks are finding that it is going to be really difficult to pull off. So, after all of these years in which electronics have been the enabler for optics in general, the industry appears to be reaching the limits on the former. Consequently, there may be no other alternative than to use optics regardless of cost, and so at some point in the way distant future, SPs may finally have to be extensively employed.

Undoubtedly, 10G will continue to have legs for a considerable amount of time. In addition, 25-gig, which has only starting to be deployed, will remain even longer as a dominant rate. Again, despite Web 2.0 firms, including Microsoft, clamoring for 50G now, its commercialization just cannot be reasonably predicted.

Even when Inphi briefed us pertaining to the announcement of its family of PAM-4 PHY ICs in August 2015, the priority for business was ranked in the following way: 40G, 100G, 400G (our views on this speed not being widespread for an extremely lengthy period are well-documented), and only then 50G. Nevertheless, we suspect that the supplier would argue that 50G per lane has been demonstrated for two years at OFC and that the last IEEE meetings in Atlanta adopted the 50G per lane as the solution for several new workgroups. While we would not find these points to be necessarily convincing for widespread usage, we have been told by a very knowledgeable contact at another company that given the materials and discontinuities as well as the incremental power of the equalization, the suspicion is that 50-gig per lane will be the last interoperable electrical signaling rate that can support more than 30dB channels – although it is probable that proprietary solutions could support higher rates.

There definitely appears to be optimism that 30-32db is possible with PAM-4 over copper. Moreover, electrical signaling using this modulation is evidently doable even with a 200G I/O depending on the copper cable gauge.

[written by Mark Lutkowitz]



Your email address will not be published. Required fields are marked *