Recently, fibeReality has written about the latest catchphrase in the optics space, co-packaged optics, and mentioned the potential challenges with expense and yield, as well as other alternatives. In looking at the case for the technology, it does have some attractive aspects. The tiny chip-like optical modules are superior to COBO-like gear in that the latter is lousy on pad density. The idea with the former is that the engineer is reaching inside the pluggable module, and taking out the optical engine on the tiny printed circuit board, and then throwing away a lot of the package. While the argument can be made that the package is not the most expensive part, its assembly and testing are both a part of the cost, but most importantly, the engine is only driving about two centimeters away from the switch, and so, there is a significant reduction in both the power consumption, as well as a larger available silicon area. Thus, either a smaller chip can be produced, which would be cheaper, especially with better yield, or alternatively, there can be an increase in the switch port count. As we continue to look at the pros and cons of co-packaged optics in this article, we will render a judgement on the solution at the end.
One of the most appealing factors to us is that the interfaces do not have to be PAM4, eliminating the need for forward error correction. In dropping down from a VSR to an XSR or USR, there is utilization of NRZ.
In producing this special optical module, and providing it with features that make it look chip-like, it would be soldered down. However, a possible cause of inertia is that some people may be very concerned about putting an LGA down. While proponents of co-packaging concede that there may be a desire for a field-replaceable gear, they assert that it would be fairly impractical in opening up the whole device, and taking the heat sink off the processor or the switch -- not to mention such activity rarely takes place in the field.
Still, this last point of discussion highlights a major hurdle regarding the need for a lot of packaging development. In terms of soldering, it has not only been done on multi-chip modules, but there is also experience with multi-component carrier, which involves packages of heterogeneous technologies.
Then there is trying to figure out the order of assembly. Does the designer put the big switch ASIC down, test and verify it, and then place the optics? What if there is then a gaffe found on one of them? How is it fixed – or should the optics be put down first?
Therefore, re-workability also certainly becomes an issue. When there is a costly switch chip surrounded with even more expensive optics, and it does not yield, there will be a lot of money invested in that assembly, and so, throwing that substrate away will not be a viable option.
Also, there are the standard reliability matters. Some advocates contend that they can be solved through sparing.
In taking another look at copper competing with co-packaged optics, it appears quite conceivable that a company like Samtec can get imaginative in bringing power to the top of the package – maybe even just 100 amps. It would be enough to free up a lot of power pins on the bottom of the package, and allow for an increase in the port count that way.
Our verdict would definitely be a summary judgement. It is not hard to see why co-packaged optics has failed to be applied commercially, yet, despite work being done on it as long as eight years ago. We agree with the cynics that it is just another buzz word for COBO, just in a different form factor – and we have not been bullish about COBO.
The most optimistic scenario is that Broadcom goes to 100G electrical in what some individuals in the industry are calling, “Tomahawk 4,” and the company may have to use co-packaged optics to get on and off. The problem is that it is not out of the question that widespread availability of that data rate electrically could be take as long as 2023.
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[written by Mark Lutkowitz]